The present invention relates to a semiconductor multilevel interconnect structures exhibiting a low RC time delay and which take less time to fabricate. More particularly, the present invention relates to a semiconductor multilevel interconnect structure made of metals having a low resistivity and insulators having a low dielectric constant k, and to a method of fabricating the multilevel interconnect structure with a low-k dielectric.
It is common in the semiconductor art to use layers of metal, polysilicon, or another conductor to conduct current between various semiconductor structures with an integrated circuit, and to external terminals for the integrated circuit, by means of conductive vias.
When a metal is used to form the interconnect layers of conductors, the metal is usually deposited on the semiconductor by sputtering, chemical vapor deposition (CVD), or evaporation. The CVD process forms a non-volatile solid film on a substrate by the reaction of vapor phase chemicals that contain the desired constituents. The metals that are commonly used for the interconnect layers are aluminum and its alloys, although other conductive metals and materials can also be used, with copper being a recent preference. The metal layers are typically deposited over dielectric materials, such as silicon dioxide. Parallel plate capacitive effects can be observed with a conductive interconnect structure. The capacitance for adjacent conductive layers can be represented as:
  C  =                                          ɛ            0                    ⁢                      ɛ            ins                    ⁢          A                                    D                            where D=SiO2 thickness         A=Area of plates (adjacent conductors)         ∈o=Permittivity of free space         ∈ins=Relative Permittivity of SiO2         
This capacitance at a metal interconnected plate increases as the density of the integrated circuits increases. Also, the line resistance due to the metal layers increases as the density of the integrated circuits increases. The resistance of a sheet of conducting material is given as:
      R    s    =            r      ⁢                          ⁢      L              t      ⁢                          ⁢      W                      where r=Material resistivity         L=Material length         t=Material thickness         W=Material width        
Thus, the time delay caused by the product of the line resistance and the capacitance (RC delay) becomes increasingly critical as device size decreases and which circuit speed increases.
An attempt to reduce the capacitance association with interconnect layers deposited on dielectric materials is shown in Togo et al., “A Gate-side Air-gap Structure (GAS) to Reduce the Parasitic Capacitance in MOSFETs”, 1996 Symposium on VLSI Technology, Digest of Technical Papers, pp. 38–39. Togo et al outlines a transistor structure in which the sidewalls of the gate structure are surrounded by an air gap. A silicon nitride sidewall is first fabricated that surrounds the gate. A layer of silicon dioxide is formed around the silicon nitride sidewall. The silicon nitride sidewall is removed by a wet etching process to form an air gap between the gate structure and the silicon dioxide.
Another attempt to reduce the capacitance associated with interconnect layers deposited on silicon is shown in Anand et al, “NURA: A Feasible, Gas-Dielectric Interconnect Process”, 1996 Symposium on VLSI Technology, Digest of Technical Papers, pp. 83–83. Anand et al outlines a metal interconnect structure in which layers of a gas are formed between thin layers of silicon dioxide. The thin layers of silicon dioxide have metal interconnect layers deposited on them. The process begins when layers of carbon are formed on a surface and trenches are formed for future interconnections. An interconnect metal layer is formed in the carbon trenches and a thin layer of silicon dioxide is sputter-deposited. Oxygen is then furnace ashed into the carbon layer through diffusion and the oxygen reacts with the carbon to form carbon dioxide. This process is repeated to form the interconnect structure of the device under fabrication.
Although Togo et al claims to reduce the capacitance associated with the interconnect layers by reducing the dielectric constant of the materials between the interconnect layers, Togo et al only provides a low dielectric material (air) around the gate contact of a transistor. Also, Togo et al does not disclose an interconnect structure that has reduced resistivity.
Likewise, even though Anand et al claims to reduce the capacitance associated with the interconnect layers by reducing the dielectric constant of the materials between the interconnect layers, Anand et al adds complexity to the semiconductor fabrication process because carbon is used in the process, which is not typically used in the manufacture of semiconductor devices. The method of Anand et al does not disclose an interconnect structure that has reduced resistivity.
Thus, the need exists for a semiconductor interconnect structure with reduced capacitance and reduced resistivity, thereby decreasing the RC time delay associated with the interconnect layers. The need also exists for a method of fabricating such a structure using standard fabrication steps in conjunction with commercially available processing equipment.
Also, steady improvements in integrated circuit density and performance have been achieved over the past two decades by transistor scaling. While the scaling continues to be necessary, metal interconnects are now becoming a significant limiting factor and are as important as transistors in determining ULSI density and performance. As discussed by M. T. Bohr in “Interconnect Scaling-The Real Limiter to High Performance ULSI”, 1995 IEDM Technical Digest, p. 241–244, each technology generation represents a 0.7× reduction in feature size, and interconnect delay degrades at a rate of 2× per generation assuming a constant metal aspect ratio and no change in conductor or dielectric materials.
As the feature size goes down so does insulator thickness so the interconnect capacitance remains the same while the wiring resistance doubles. Interconnect delay for large high-frequency chips is already a significant portion of the clock cycle time and will soon exceed the cycle time requirements if traditional interconnect scaling is continued.
Also the increasing density/complexity of circuits and speed of operation result in excessive power dissipation in digital switching and clocking circuits. The power dissipation is approximately represented by:Power˜CV2f                where C=the capacitance of the clock line,         V=the voltage swing, and         f=the clock frequency.        
As noted by L. Maliniak, “DAC attacks designer issues”, Electronic Design, vol. 43, p. 66, 12 Jun. 1995, clock distribution can account for up to 40% of the total power dissipation in high-performance wireless computing and communication systems.
Similar considerations apply in calculating the power dissipation of digital switching circuits.